Booth Array Multiplier

This IP core provides a resource efficient implementation of a Booth Array Multiplier for Xilinx FPGAs as proposed in:

M. Kumm, S. Abbas, and P. Zipf, An Efficient Softcore Multiplier Architecture for Xilinx FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2015, pp. 18–25, DOI

The Project is hosted at opencores.org.

Download documentation

Download complete package