Publications

Thesis

  Kumm, M.
Dissertation Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays,
Springer Wiesbaden, Germany
2016 (PhD defense: October 30th, 2015)
ISBN 978-3-658-13323-8

see Table of Contents and ask me for a copy of a chapter

or Buy at springer.com or Buy at amazon.com

International Journal Papers

  1. M. Kumm, M. Hardieck and P. Zipf, Optimization of Constant Matrix Multiplication with Low Power and High Throughput, IEEE Transactions on Computers, accepted for publication (06.05.2017), DOI
  2. K. Möller, M. Kumm, M. Garrido and P. Zipf, Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, accepted for publication (22.06.2017), DOI
  3. M. Kumm, M. Garrido, O. Gustafsson and P. Zipf, Optimal Constant Coefficient Multiplication using Ternary Adders, IEEE Transactions on Circuits and Systems II: Express Briefs, accepted for publication (21.10.2016), DOI
  4. K. Möller, M. Kumm, M. Kleinlein and P. Zipf, Reconfigurable Constant Multiplication for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(6), 927-–937 DOI
  5. M- Kumm and P. Zipf, Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”, International Journal of Reconfigurable Computing (Hindawi), 1–3, 2016, DOI
  6. M. Garrido, P. Källström, M. Kumm, and O. Gustafsson, CORDIC II: A New Improved CORDIC Algorithm, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 186–190, 2016, DOI
  7. M. Kumm, D. Fanghänel, K. Möller, P. Zipf, and U. Meyer-Baese, FIR Filter Optimization for Video Processing on FPGAs, EURASIP Journal on Advances in Signal Processing (Springer), pp. 1–18, 2013, DOI
  8. M. Kumm, H. Klingbeil, and P. Zipf, An FPGA-Based Linear All-Digital Phase-Locked Loop, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2487–2497, 2010, DOI
  9. H. Klingbeil, B. Zipfel, M. Kumm, and P. Moritz, A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons, IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2604–2610, 2007, DOI

International Conference Proceedings

  1. P. Sittel, K. Möller, M. Kumm, P. Zipf, B. Pasca and M. Jervis, Model-Based Hardware Design based on Compatible Sets of Isomorphic Subgraphs, accepted for presentation at the IEEE International Conference on Field-Programmable Technology (FPT), 2017
  2. M. Kumm, M. Istoan and P. Zipf, Resource Optimal Design of Large Multipliers for FPGAs, IEEE International Conference on Computer Arithmetic, 2017, pp. 131–138, DOI
  3. M. Kumm, M. Kleinlein, and P. Zipf, Efficient Sum of Absolute Difference Computation on FPGAsternational Conference on Field Programmable Logic and Application (FPL), 2016, pp. 1-4, DOI
  4. U. Meyer-Baese, H. Muddu, S. Schinhaerl, M. Kumm, and P. Zipf, Real-time Fetal ECG System Design using Embedded Microprocessors, SPIE Commercial + Scientific Sensing and Imaging, vol. 9871, pp. 987106-1–987106-14, May 2016, DOI
  5. M. Faust, M. Kumm, C.-H. Chang, and P. Zipf, Efficient Structural Adder Pipelining in Transposed Form FIR Filters, IEEE International Conference on Digital Signal Processing (DSP), 2015, pp. 311-314, DOI
  6. M. Kumm, S. Abbas, and P. Zipf, An Efficient Softcore Multiplier Architecture for Xilinx FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2015, pp. 18–25, DOI
  7. K. Möller, M. Kumm, M. Kleinlein, and P. Zipf, Pipelined Reconfigurable Multiplication with Constants on FPGAs, IEEE International Conference on Field Programmable Logic and Application (FPL), 2014, pp. 1–6, DOI
  8. M. Kumm and P. Zipf, Pipelined Compressor Tree Optimization Using Integer Linear Programming, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8, DOI
  9. M. Kumm, M. Hardieck, J. Willkomm, P. Zipf, and U. Meyer-Baese, Multiple Constant Multiplication with Ternary Adders, IEEE International Conference on Field Programmable Logic and Application (FPL), 2013, pp. 1–8, DOI
  10. M. Kumm, K. Möller, and P. Zipf, Partial LUT Size Analysis in Distributed Arithmetic FIR Filters on FPGAs, IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2054–2057, DOI
  11. M. Kumm, K. Möller, and P. Zipf, Reconfigurable FIR Filter Using Distributed Arithmetic on FPGAs, IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2058–2061, DOI
  12. U. Meyer-Baese, G. Botella, D. Romero, and M. Kumm, Optimization of High Speed Pipelining in FPGA-Based FIR Filter Design Using Genetic Algorithm, Proceedings of SPIE, 2012, pp. 1–12, DOI
  13. M. Kumm and P. Zipf, Hybrid Multiple Constant Multiplication for FPGAs, IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012, pp. 556–559, DOI
  14. M. Kunz, M. Kumm, M. Heide, and P. Zipf, Area Estimation of Look-Up Table Based Fixed-Point Computations on the Example of a Real-Time High Dynamic Range Imaging System, IEEE International Conference on Field Programmable Logic and Application (FPL), 2012, pp. 591–594, DOI
  15. M. Kumm, K. Liebisch, and P. Zipf, Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision, IEEE International Conference on Field Programmable Logic and Application (FPL), 2012, pp. 255–261, DOI
  16. M. Kumm, P. Zipf, M. Faust, and C.-H. Chang, Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication, IEEE International Symposium on Circuits and Systems (ISCAS), 2012, pp. 49–52, DOI
  17. M. Kumm and P. Zipf, High Speed Low Complexity FPGA-Based FIR Filters Using Pipelined Adder Graphs, IEEE International Conference on Field-Programmable Technology (FPT), 2011, pp. 1–4, DOI
  18. M. Mehler, H. Klingbeil, U. Laier, K.-P. Ningel and M. Kumm, The Damping of Longitudinal Quadrupole Oscillations at GSI, Particle Accelerator Conference (PAC), 2009, S.2195–2197
  19. M. Kumm and S. Sanjari, Digital Hilbert Transformers for FPGA-Based Phase-Locked Loops, IEEE International Conference on Field Programmable Logic and Application (FPL), 2008, pp. 251–256, DOI

Workshop Papers

  1. P. Sittel, M. Kumm, K. Möller, M. Hardieck and P. Zipf, High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017, pp. 7–12
  2. K. Möller, M. Kumm, C.-F. M{\”uller, and P. Zipf, Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuitsternational Workshop on FPGAs for Software Programmers (FSP), 2015, pp. 7–12, arxiv.org
  3. K. Möller, M. Kumm, B. Barschtipan, and P. Zipf, Dynamically Reconfigurable Constant Multiplication on FPGAs., Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014, pp. 159–169.
  4. M. Kumm and P. Zipf, Efficient High Speed Compression Trees on Xilinx FPGAs, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014, pp. 171–182.
  5. M. Kumm, K. Möller, and P. Zipf, Dynamically Reconfigurable FIR Filter Architectures with Fast Reconfiguration, International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2013, pp. 1–8, DOI
  6. A. Guntoro, P. Zipf, O. Soffke, H. Klingbeil, M. Kumm and M. Glesner, Implementation of Realtime and Highspeed Phase Detector on FPGA, International Workshop on Reconfigurable Computing (ARC), 2006, Vol. 3985, pp. 1–11, DOI

Submitted Patents

  1. M. Kumm und P Zipf, Verfahren zum Multiplizieren zweier Binärzahlen mit einer programmierbaren Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, 2015, DPMA
  1. M. Kumm und P Zipf, Verfahren zum Berechnen von Funktionswerten mit einer Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, submitted 2017

Non-Scientific Publications

  1. M. Kumm, Preisgünstige Eigenbau-Lötstation mit SMD-Lötspitze von Weller, Funkamateur, 07/2014
  2. M. Kumm, C. Valens, S. Malekar, An SMD solder station made from bits and pieces! Platino Solder Station, Elektor 07-08/2015
  3. M. Kumm, C. Valens, S. Malekar, Bauen Sie Ihre eigene SMD-Lötstation! Platino-Lötkolben, Elektor (Germany) 07-08/2015
01Publications.txt · Last modified: 2017/10/18 09:18 by Martin Kumm  (login)