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Publications
Thesis
Kumm, M. Dissertation Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays, Springer Wiesbaden, Germany 2016 (PhD defense: October 30th, 2015) ISBN 978-3-658-13323-8 see Table of Contents and ask me for a copy of a chapter |
International Journal Papers
- S. Tridgell, M. Kumm, M. Hardieck, D. Boland, D. J. M. Moss, P. Zipf, P. and P. H. W. Leong, Unrolling Ternary Neural Networks, accepted for publication in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2019
- J. Faraone, M. Kumm, M. Hardieck, L. Xueyuan, D. Boland, and P. H. W. Leong, AddNet: Deep Neural Networks using FPGA-Optimized Multipliers, accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (VLSI)
- K. Möller, M. Kumm, M. Garrido and P. Zipf, Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, issue 3, 710–714, 2018, DOI
- M. Kumm, M. Garrido, O. Gustafsson and P. Zipf, Optimal Constant Coefficient Multiplication using Ternary Adders, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 7, July 2018, DOI, preprint (copyright IEEE), slides from ISCAS'17
- K. Möller, M. Kumm, M. Kleinlein and P. Zipf, Reconfigurable Constant Multiplication for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(6), 927-–937 DOI
- M- Kumm and P. Zipf, Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”, International Journal of Reconfigurable Computing (Hindawi), 1–3, 2016, DOI
- M. Garrido, P. Källström, M. Kumm, and O. Gustafsson, CORDIC II: A New Improved CORDIC Algorithm, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 186–190, 2016, DOI
- M. Kumm, D. Fanghänel, K. Möller, P. Zipf, and U. Meyer-Baese, FIR Filter Optimization for Video Processing on FPGAs, EURASIP Journal on Advances in Signal Processing (Springer), pp. 1–18, 2013, DOI
- H. Klingbeil, B. Zipfel, M. Kumm, and P. Moritz, A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons, IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2604–2610, 2007, DOI
International Conference Proceedings
- P. Sittel, N. Fiege, M. Kumm and P. Zipf, Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling, accepted for presentation at the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2019
- P. Sittel, J. Wickerson, M. Kumm and P. Zipf, Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design, Accepted for presentation at the Asia and South Pacific Design Automation Conference (ASP-DAC), 2019
- G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, Efficient Error-Tolerant Quantized Neural Network Accelerators, IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019, received the best paper award
- F. de Dinechin, S. Filip, L. Forget and M. Kumm, Table-Based versus Shift-And-Add Constant Multipliers for FPGAs accepted for presentation at the IEEE Symposium on Computer Arithmetic (ARITH), 2019, preprint
- J. Oppermann, P. Sittel, M. Kumm, M. Reuter-Oppermann, A. Koch, O. Sinnen, Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling, accepted for presentation at the European Conference on Parallel Processing (EUROPAR), 2019, preprint
- M. Hardieck, M. Kumm, P. Sittel and P. Zipf, Constant Matrix Multiplication with Ternary Adders, accepted for Presentation at the 25th IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. preprint
- P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, ILP-based Modulo Scheduling and Binding for Register Minimization, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 preprint (copyright IEEE)
- M. Kumm, O. Gustafson, F. de Dinechin, J. Kappauf and P. Zipf, Karatsuba with Rectangular Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2018, preprint (copyright IEEE) received the best paper award
- U. Meyer-Baese, H. Muddu, S. Schinhaerl, M. Kumm, and P. Zipf, Real-time Fetal ECG System Design using Embedded Microprocessors, SPIE Commercial + Scientific Sensing and Imaging, vol. 9871, pp. 987106-1–987106-14, May 2016, DOI
- U. Meyer-Baese, G. Botella, D. Romero, and M. Kumm, Optimization of High Speed Pipelining in FPGA-Based FIR Filter Design Using Genetic Algorithm, Proceedings of SPIE, 2012, pp. 1–12, DOI
- M. Kunz, M. Kumm, M. Heide, and P. Zipf, Area Estimation of Look-Up Table Based Fixed-Point Computations on the Example of a Real-Time High Dynamic Range Imaging System, IEEE International Conference on Field Programmable Logic and Application (FPL), 2012, pp. 591–594, DOI, preprint (copyright IEEE)
- M. Mehler, H. Klingbeil, U. Laier, K.-P. Ningel and M. Kumm, The Damping of Longitudinal Quadrupole Oscillations at GSI, Particle Accelerator Conference (PAC), 2009, S.2195–2197
Workshop Papers
- G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, Analysis of SEU susceptibility of Quantized Neural Network Hardware Accelerators via Error Injection, accepted for presentation at the IEEE International Workshop on Automotive Reliability Test ART, 2019
- P. Sittel, J. Oppermann, M. Kumm, A. Koch and P. Zipf, HatScheT: A Contribution to Agile HLS, accepted for presentation at the FPGAs for Software Programmers (FSP) Workshop, Dublin August 2018, preprint
- P. Sittel, T. Schönwälder, M. Kumm and P. Zipf, ScaLP: A Light-Weighted (MI)LP-Library, 21. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), March 2018, Tübingen. preprint
- P. Sittel, M. Kumm, K. Möller, M. Hardieck and P. Zipf, High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017, pp. 7–12, preprint
- K. Möller, M. Kumm, B. Barschtipan, and P. Zipf, Dynamically Reconfigurable Constant Multiplication on FPGAs., Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014, pp. 159–169, preprint
- A. Guntoro, P. Zipf, O. Soffke, H. Klingbeil, M. Kumm and M. Glesner, Implementation of Realtime and Highspeed Phase Detector on FPGA, International Workshop on Reconfigurable Computing (ARC), 2006, Vol. 3985, pp. 1–11, DOI
Submitted Patents
- M. Kumm und P Zipf, Verfahren zum Multiplizieren zweier Binärzahlen mit einer programmierbaren Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, 2015, DPMA
- M. Kumm und P Zipf, Verfahren zum Berechnen von Funktionswerten mit einer Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, submitted 2017
Non-Scientific Publications
- M. Kumm, Preisgünstige Eigenbau-Lötstation mit SMD-Lötspitze von Weller, Funkamateur, 07/2014
- M. Kumm, C. Valens, S. Malekar, An SMD solder station made from bits and pieces! Platino Solder Station, Elektor 07-08/2015
- M. Kumm, C. Valens, S. Malekar, Bauen Sie Ihre eigene SMD-Lötstation! Platino-Lötkolben, Elektor (Germany) 07-08/2015
01Publications.1571761582.txt.gz · Last modified: 2019/10/22 18:26 by Martin Kumm (login)