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--- 01Publications [2019/11/08 09:44]
Martin Kumm
+++ 01Publications [2024/02/23 09:54] (current)
Martin Kumm
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 ======= Publications =======
-=== Thesis ===
+=== Books ===
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-<a href="http://www.springer.com/gp/book/9783658133221#">
+<a href="https://link.springer.com/book/9783031428074"><img src="https://m.media-amazon.com/images/I/61V5pib+RKL._SL1285_.jpg" style="width:40%"></a>
-<img src="https://images.springer.com/sgw/books/medium/9783658133221.jpg" style="width:80%">
+</td><td width="5%">&nbsp;</td><td style="text-align:left;">
-</a>
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-<html></td><td width="5%">&nbsp;</td><td style="text-align:left;">
+Florent de Dinechin, Martin Kumm\\
+//Application-Specific Arithmetic - Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era//\\
+Springer\\
+
+\\
+ISBN 978-3-031-42807-4 (Hardcover), 978-3-031-42808-1 (eBook)
+\\
+[[https://link.springer.com/book/9783031428074#|Buy at springer.com]]
+or
+[[https://www.amazon.de/-/en/Florent-Dinechin/dp/3031428072|Buy at amazon.com]]
+<html></td></tr><tr><td>&nbsp;</td></tr><tr><td>
+<a href="http://www.springer.com/gp/book/9783658133221#"><img src="https://media.springernature.com/w306/springer-static/cover-hires/book/978-3-658-13323-8" style="width:40%"></a>
+</td><td width="5%">&nbsp;</td><td style="text-align:left;">
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 Kumm, M.\\
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  \\
 see [[http://www.springer.com/cda/content/document/cda_downloaddocument/9783658133221-t1.pdf?SGWID=0-0-45-1557872-p179912489|Table of Contents]] and [[06Contact|ask me for a copy of a chapter]]
 or [[http://www.springer.com/gp/book/9783658133221#|Buy at springer.com]]
 or
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 === International Journal Papers ===
-  - S. Tridgell, M. Kumm, M. Hardieck, D. Boland, D. J. M. Moss, P. Zipf, P. and P. H. W.  Leong, //Unrolling Ternary Neural Networks//, accepted for publication in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2019
-  - J. Faraone, M. Kumm, M. Hardieck, L. Xueyuan, D. Boland, and P. H. W. Leong, //AddNet: Deep Neural Networks using FPGA-Optimized Multipliers//, accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (VLSI)
+  - N. Fiege, M. Kumm, P. Zipf, //Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability//, IEEE Transactions on Circuits and Systems I: Regular Papers, 71(1), 249-261, 2024 [[http://martin-kumm.de/preprints/2023_TACSI_Fiege.pdf|preprint]] (copyright IEEE) [[https://doi.org/10.1109/tcsi.2023.3327814|DOI]]
+  - A. Böttcher and M. Kumm, //Towards Globally Optimal Design of Multipliers for FPGAs//, IEEE Transactions on Computers, 72(5), 2023, 1261-1273, 2023 [[http://martin-kumm.de/preprints/2023_TC_Boettcher.pdf|preprint]]  (copyright IEEE) [[https://doi.org/10.1109/TC.2023.3238128|DOI]]
+  - M. Kumm, A. Volkova and S. I. Filip, //Design of Optimal Multiplierless FIR Filters with Minimal Number of Adders//, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 42, 658–671, 2023 [[https://hal.archives-ouvertes.fr/hal-02392522v4/document|preprint]], [[https://doi.org/10.1109/tcad.2022.3179221|DOI]]
+  - R. Garcia, A. Volkova, M. Kumm, A. Goldsztejn and J. Kühle, //Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders//, IEEE Transactions on Signal Processing, 70, 1673-1686, 2022, [[https://arxiv.org/abs/2108.01565|preprint]], [[https://doi.org/10.1109/TSP.2022.3161158|DOI]]
+  - S. Tridgell, M. Kumm, M. Hardieck, D. Boland, D. J. M. Moss, P. Zipf, P. and P. H. W.  Leong, //Unrolling Ternary Neural Networks//, ACM Transactions on Reconfigurable Technology and Systems, 12(4), 1–23, 2019, [[http://doi.org/10.1145/3359983|DOI]]
+  - J. Faraone, M. Kumm, M. Hardieck, L. Xueyuan, D. Boland, and P. H. W. Leong, //AddNet: Deep Neural Networks using FPGA-Optimized Multipliers//, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 28(1), 115-128, 2020,  [[https://doi.org/10.1109/TVLSI.2019.2939429|DOI]]
   - M. Garrido, K. Möller, M. Kumm, //World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s//, IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 66 , Issue 4, 2019, [[https://doi.org/10.1109/TCSI.2018.2886626|DOI]], [[http://martin-kumm.de/preprints/2019_TCASI_Garrido.pdf|preprint]] (copyright IEEE)
   - M. Kumm, //Optimal Constant Multiplication using Integer Linear Programming//, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 5, May 2018, [[https://doi.org/10.1109/TCSII.2018.2823780|DOI]], [[http://martin-kumm.de/preprints/2018_TCASII_Kumm.pdf|preprint]] (copyright IEEE)
@@ Line 35: / Line 50: @@
   - M. Kumm, M. Hardieck and P. Zipf, //Optimization of Constant Matrix Multiplication with Low Power and High Throughput//, IEEE Transactions on Computers, Volume 66, Issue 12, 2017, [[https://doi.org/10.1109/TC.2017.2701365|DOI]], [[http://martin-kumm.de/preprints/2017_TC_kumm.pdf|preprint]] (copyright IEEE)
   - K. Möller, M. Kumm, M. Kleinlein and P. Zipf, //Reconfigurable Constant Multiplication for FPGAs//, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(6), 927-–937 [[http://doi.org/10.1109/TCAD.2016.2614775|DOI]]
-  - M- Kumm and P. Zipf, //Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs"//, International Journal of Reconfigurable Computing (Hindawi), 1--3, 2016, [[http://dx.doi.org/10.1155/2016/3015403|DOI]]
+  - M. Kumm and P. Zipf, //Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs"//, International Journal of Reconfigurable Computing (Hindawi), 1--3, 2016, [[http://dx.doi.org/10.1155/2016/3015403|DOI]]
   - M. Garrido, P. Källström, M. Kumm, and O. Gustafsson, //CORDIC II: A New Improved CORDIC Algorithm//, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 186--190, 2016, [[https://doi.org/10.1109/TCSII.2015.2483422|DOI]]
   - M. Kumm, D. Fanghänel, K. Möller, P. Zipf, and U. Meyer-Baese, //FIR Filter Optimization for Video Processing on FPGAs//, EURASIP Journal on Advances in Signal Processing (Springer), pp. 1--18, 2013, [[https://doi.org/10.1186/1687-6180-2013-111|DOI]]
   - M. Kumm, H. Klingbeil, and P. Zipf, //An FPGA-Based Linear All-Digital Phase-Locked Loop//, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2487--2497, 2010, [[https://doi.org/10.1109/TCSI.2010.2046237|DOI]], [[http://martin-kumm.de/preprints/2010_TCAS-I_Kumm.pdf|preprint]] (copyright IEEE)
   - H. Klingbeil, B. Zipfel, M. Kumm, and P. Moritz, //A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons//, IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2604--2610, 2007, [[https://doi.org/10.1109/TNS.2007.909666|DOI]]
 === International Conference Proceedings  ===
-  - P. Sittel, N. Fiege, M. Kumm and P. Zipf, //Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling//, accepted for presentation at the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2019
-  - P. Sittel, J. Wickerson, M. Kumm and P. Zipf, //Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design//, Accepted for presentation at the Asia and South Pacific Design Automation Conference (ASP-DAC), 2019
-  - G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, //Efficient Error-Tolerant Quantized Neural Network Accelerators//, IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019,  [[http://martin-kumm.de/preprints/2019_DFT_Gambardella.pdf|preprint]] **received the best paper award**
+  - A. Volkova, R. Garcia, F. de Dinechin, M. Kumm, //Hardware-optimal digital FIR filters: one ILP to rule them all and in faithfulness bind them//, Asilomar Conference on Signals, Systems and Computers, 2023 [[http://martin-kumm.de/preprints/2023_Asilomar_Volkova.pdf|preprint]] (copyright IEEE)
-  - F. de Dinechin, S. Filip, L. Forget and M. Kumm, //Table-Based versus Shift-And-Add Constant Multipliers for FPGAs// accepted for presentation at the IEEE Symposium on Computer Arithmetic (ARITH), 2019,  [[http://martin-kumm.de/preprints/2019_ARITH_Dinechin.pdf|preprint]]
+  - M. Hardieck, T. Habermann, F. Wagner, M. Mecik, M. Kumm, P. Zipf, //More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers//, IEEE International Symposium on Circuits and Systems (ISCAS), 2023, [[http://martin-kumm.de/preprints/2022_Hardieck.pdf|preprint]] (copyright IEEE), [[https://doi.org/10.1109/ISCAS46773.2023.10181827|DOI]]
-  - J. Oppermann, P. Sittel, M. Kumm, M. Reuter-Oppermann, A. Koch, O. Sinnen, //Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling//, accepted for presentation at the European Conference on Parallel Processing (EUROPAR), 2019,  [[http://martin-kumm.de/preprints/2019_EUROPAR_Oppermann.pdf|preprint]]
+  - T. Habermann, J. Kühle, M. Kumm and A. Volkova, //Hardware-Aware Quantization for Multiplierless Neural Network Controllers//, Asia Pacific Conference on Circuits and Systems (APCCAS), 2022, [[https://hal.archives-ouvertes.fr/hal-03827660/document|preprint]], [[https://doi.org/10.1109/APCCAS55924.2022.10090271|DOI]]
-  - M. Hardieck, M. Kumm, K. Möller and P. Zipf, //Reconfigurable Convolutional Kernels for Neural Networks on FPGAs//, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Array (FPGA), Monterey February 2019, [[https://doi.org/10.1145/3289602.3293905|DOI]], [[http://martin-kumm.de/preprints/2019_FPGA_Hardieck.pdf|preprint]] (copyright ACM)
+  - A. Böttcher, M. Kumm, F. de. Dinechin, //Resource Optimal Squarers for FPGAs// IEEE International Conference on Field Programmable Logic and Application (FPL), 2022, [[http://martin-kumm.de/preprints/2022_FPL_Boettcher.pdf|preprint]], [[https://doi.org/10.1109/FPL57034.2022.00018|DOI]]
-  - M. Hardieck, M. Kumm, P. Sittel and P. Zipf, //Constant Matrix Multiplication with Ternary Adders//, accepted for Presentation at the 25th IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. [[http://martin-kumm.de/preprints/2018_ICECS_Hardieck.pdf|preprint]]
+  - R. Garcia, A. Volkova, M. Kumm, //Truncated Multiple Constant Multiplication with Minimal Number of Full Adders//, IEEE International Symposium on Circuits and Systems (ISCAS), 2022, [[https://hal.science/hal-03582935/document|preprint]], [[https://doi.org/10.1109/ISCAS48785.2022.9937441|DOI]]
-  - P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, //ILP-based Modulo Scheduling and Binding for Register Minimization//, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 [[http://martin-kumm.de/preprints/2018_FPL_Sittel.pdf|preprint]] (copyright IEEE)
+  - A. Böttcher, M. Kumm, F. de. Dinechin, //Resource Optimal Truncated Multipliers for FPGAs//, IEEE Symposium on Computer Arithmetic (ARITH), 2021 [[https://hal.inria.fr/hal-03220290/document|preprint]]
-  - M. Kumm, O. Gustafson, F. de Dinechin, J. Kappauf and P. Zipf, //Karatsuba with Rectangular Multipliers for FPGAs//, IEEE Symposium on Computer Arithmetic (ARITH), 2018, [[http://martin-kumm.de/preprints/2018_ARITH_kumm.pdf|preprint]] (copyright IEEE) **received the best paper award**
+  - L. Sommer, L. Weber, M. Kumm, A. Koch, //Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs//, International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2020, [[http://doi.org/10.1109/FCCM48280.2020.00020|DOI]] **received the best paper award**
+  - A. Böttcher, K. Kullmann, M. Kumm, //Heuristics for the Design of Large Multipliers for FPGAs//, IEEE Symposium on Computer Arithmetic (ARITH), 2020 [[https://doi.org/10.1109/ARITH48897.2020.00012|DOI]] [[http://martin-kumm.de/preprints/2020_ARITH_Boettcher.pdf|preprint]]
+  - P. Sittel, J. Wickerson, M. Kumm and P. Zipf, //Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design//, Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, [[https://doi.org/10.1109/ASP-DAC47756.2020.9045616|DOI]] **nominated as best paper award candidate**
+  - P. Sittel, N. Fiege, M. Kumm and P. Zipf, //Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling//, International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2019, [[https://doi.org/10.1109/ReConFig48160.2019.8994768|DOI]] [[http://martin-kumm.de/preprints/2019_Reconfig_Sittel.pdf|preprint]]
+  - G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, //Efficient Error-Tolerant Quantized Neural Network Accelerators//, IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019,  [[http://martin-kumm.de/preprints/2019_DFT_Gambardella.pdf|preprint]] [[https://doi.org/10.1109/DFT.2019.8875314|DOI]] **received the best paper award**
+  - F. de Dinechin, S. Filip, L. Forget and M. Kumm, //Table-Based versus Shift-And-Add Constant Multipliers for FPGAs//, IEEE Symposium on Computer Arithmetic (ARITH), 2019,  [[http://martin-kumm.de/preprints/2019_ARITH_Dinechin.pdf|preprint]] [[https://doi.org/10.1109/ARITH.2019.00037|DOI]]
+  - J. Oppermann, P. Sittel, M. Kumm, M. Reuter-Oppermann, A. Koch, O. Sinnen, //Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling//, European Conference on Parallel Processing (EUROPAR), 2019,  [[http://martin-kumm.de/preprints/2019_EUROPAR_Oppermann.pdf|preprint]], [[https://doi.org/10.1007/978-3-030-29400-7_13|DOI]]
+  - M. Hardieck, M. Kumm, K. Möller and P. Zipf, //Reconfigurable Convolutional Kernels for Neural Networks on FPGAs//, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey February 2019, [[http://martin-kumm.de/preprints/2019_FPGA_Hardieck.pdf|preprint]] (copyright ACM), [[https://doi.org/10.1145/3289602.3293905|DOI]]
+  - M. Hardieck, M. Kumm, P. Sittel and P. Zipf, //Constant Matrix Multiplication with Ternary Adders//, IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. [[http://martin-kumm.de/preprints/2018_ICECS_Hardieck.pdf|preprint]], [[https://doi.org/10.1109/ICECS.2018.8617860|DOI]]
+  - P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, //ILP-based Modulo Scheduling and Binding for Register Minimization//, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 [[http://martin-kumm.de/preprints/2018_FPL_Sittel.pdf|preprint]] (copyright IEEE), [[https://doi.org/10.1109/FPL.2018.00053|DOI]]
+  - M. Kumm, O. Gustafson, F. de Dinechin, J. Kappauf and P. Zipf, //Karatsuba with Rectangular Multipliers for FPGAs//, IEEE Symposium on Computer Arithmetic (ARITH), 2018, [[http://martin-kumm.de/preprints/2018_ARITH_kumm.pdf|preprint]] (copyright IEEE) **received the best paper award**, [[https://doi.org/10.1109/ARITH.2018.8464809|DOI]]
   - P. Sittel, K. Möller, M. Kumm, P. Zipf, B. Pasca and M. Jervis, //Model-Based Hardware Design based on Compatible Sets of Isomorphic Subgraphs//, IEEE International Conference on Field-Programmable Technology (FPT), 2017, [[http://doi.org/10.1109/FPT.2017.8280140|DOI]], [[http://martin-kumm.de/preprints/2017_FPT_Sittel.pdf|preprint]] (copyright IEEE)
-  - M. Kumm, M. Istoan and P. Zipf, //Resource Optimal Design of Large Multipliers for FPGAs//, IEEE International Conference on Computer Arithmetic, 2017, pp. 131--138, [[https://doi.org/10.1109/ARITH.2017.35|DOI]], [[http://martin-kumm.de/preprints/2017_ARITH_kumm.pdf|preprint]] (copyright IEEE), [[http://martin-kumm.de/slides/2017_07_25_ARITH.pdf|slides]]
+  - M. Kumm, J. Kappauf, M. Istoan and P. Zipf, //Resource Optimal Design of Large Multipliers for FPGAs//, IEEE International Conference on Computer Arithmetic, 2017, pp. 131--138, [[https://doi.org/10.1109/ARITH.2017.35|DOI]], [[http://martin-kumm.de/preprints/2017_ARITH_kumm.pdf|preprint]] (copyright IEEE), [[http://martin-kumm.de/slides/2017_07_25_ARITH.pdf|slides]]
   - M. Kumm, M. Kleinlein, and P. Zipf, //Efficient Sum of Absolute Difference Computation on FPGAs//IEEE International Conference on Field Programmable Logic and Application (FPL), 2016, pp. 1-4, [[https://doi.org/10.1109/FPL.2016.7577374|DOI]], [[http://martin-kumm.de/preprints/2016_FPL_Kumm.pdf|preprint]] (copyright IEEE), [[http://martin-kumm.de/slides/2016_09_01_FPL.pdf|slides]]
   - U. Meyer-Baese, H. Muddu, S. Schinhaerl, M. Kumm, and P. Zipf, //Real-time Fetal ECG System Design using Embedded Microprocessors//, SPIE Commercial + Scientific Sensing and Imaging, vol. 9871, pp. 987106-1--987106-14, May 2016, [[http://dx.doi.org/10.1117/12.2224256|DOI]]
@@ Line 73: / Line 99: @@
 === Workshop Papers  ===
-  - G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, //Analysis of SEU susceptibility of Quantized Neural Network Hardware Accelerators via Error Injection//, accepted for presentation at the IEEE International Workshop on Automotive Reliability Test ART, 2019
+  - G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, //Analysis of SEU susceptibility of Quantized Neural Network Hardware Accelerators via Error Injection//, IEEE International Workshop on Automotive Reliability Test ART, 2019
-  - P. Sittel, J. Oppermann, M. Kumm, A. Koch and P. Zipf, //HatScheT: A Contribution to Agile HLS//, accepted for presentation at the FPGAs for Software Programmers (FSP) Workshop, Dublin August 2018, [[http://martin-kumm.de/preprints/2018_FSP_Sittel.pdf|preprint]]
+  - P. Sittel, J. Oppermann, M. Kumm, A. Koch and P. Zipf, //HatScheT: A Contribution to Agile HLS//, FPGAs for Software Programmers (FSP) Workshop, Dublin August 2018, [[http://martin-kumm.de/preprints/2018_FSP_Sittel.pdf|preprint]]
   - P. Sittel, T. Schönwälder, M. Kumm  and P. Zipf, //ScaLP: A Light-Weighted (MI)LP-Library//,  21. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), March 2018, Tübingen. [[http://martin-kumm.de/preprints/2018_MBMV_Sittel.pdf|preprint]]
   - P. Sittel, M. Kumm, K. Möller, M. Hardieck and P. Zipf, //High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits//, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017, pp. 7--12, [[http://martin-kumm.de/preprints/2017_MBMV_Sittel.pdf|preprint]]