Ternary Adder

This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing

s = x + y + z

for the Altera and Xilinx platforms. Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.

It was used in the following publications:

M. Kumm, M. Garrido, O. Gustafsson and P. Zipf, Optimal Constant Coefficient Multiplication using Ternary Adders, IEEE Transactions on Circuits and Systems II: Express Briefs, accepted for publication (21.10.2016), DOI

M. Kumm, M. Hardieck, J. Willkomm, P. Zipf, and U. Meyer-Baese, Multiple Constant Multiplication with Ternary Adders, IEEE International Conference on Field Programmable Logic and Application (FPL), 2013, pp. 1–8, DOI

The Project is hosted at opencores.org.

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04FPGA_Cores/Ternary_Adder.txt · Last modified: 2017/10/17 10:21 by Martin Kumm  (login)