DDS Synthesizer

The DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator, NCO) which produces a sinewave at the output with a specified frequency and phase (adjustable at runtime).

Only one quater of the sinewave is stored in the LUT, the rest is computed by simple operations (negating, subtraction), resulting in a reduced memory requirement.

The resolution of the frequency tuning word (FTW), the phase and the amplitude are defined seperately. Several precomputed look-up tables are provided as combinations from 8 to 16 bit phase and amplitude resolution. The frequency resolution can is defined as generic. A matlab script for generating the LUTs for different resolutions is included.

The design is fully pipelined for maximum throughput.

The Project is hosted at

Download documentation

Download complete package

The DDS Synthesizer was part of my Diploma Thesis (in German), some more information about DDS principles can be found there.

FPGA_Cores/DDS_Synthesizer.txt · Last modified: 2010/08/11 19:23 by pluto  (login)