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01Publications [2019/03/18 08:14]
Martin Kumm
01Publications [2019/08/13 15:00] (current)
Martin Kumm
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=== International Journal Papers === === International Journal Papers ===
 +  - J. Faraone, M. Kumm, M. Hardieck, L. Xueyuan, D. Boland, and P. H. W. Leong, //AddNet: Deep Neural Networks using FPGA-Optimized Multipliers//, accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (VLSI)
  - M. Garrido, K. Möller, M. Kumm, //World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s//, IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 66 , Issue 4, 2019, [[https://doi.org/10.1109/TCSI.2018.2886626|DOI]], [[http://martin-kumm.de/preprints/2019_TCASI_Garrido.pdf|preprint]] (copyright IEEE)   - M. Garrido, K. Möller, M. Kumm, //World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s//, IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 66 , Issue 4, 2019, [[https://doi.org/10.1109/TCSI.2018.2886626|DOI]], [[http://martin-kumm.de/preprints/2019_TCASI_Garrido.pdf|preprint]] (copyright IEEE)
  - M. Kumm, //Optimal Constant Multiplication using Integer Linear Programming//, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 5, May 2018, [[https://doi.org/10.1109/TCSII.2018.2823780|DOI]], [[http://martin-kumm.de/preprints/2018_TCASII_Kumm.pdf|preprint]] (copyright IEEE)   - M. Kumm, //Optimal Constant Multiplication using Integer Linear Programming//, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 5, May 2018, [[https://doi.org/10.1109/TCSII.2018.2823780|DOI]], [[http://martin-kumm.de/preprints/2018_TCASII_Kumm.pdf|preprint]] (copyright IEEE)
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=== International Conference Proceedings  === === International Conference Proceedings  ===
-  - M. Hardieck, M. Kumm, K. Möller and P. Zipf, //Reconfigurable Convolutional Kernels for Neural Networks on FPGAs//, accepted for presentation at the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Array (FPGA), Monterey February 2019, [[https://doi.org/10.1145/3289602.3293905|DOI]], [[http://martin-kumm.de/preprints/2019_FPGA_Hardieck.pdf|preprint]] (copyright ACM)+  - G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, Efficient Error-Tolerant Quantized Neural Network Accelerators. accepted for presentation at the IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 
 +  - F. de Dinechin, S. Filip, L. Forget and M. Kumm, //Table-Based versus Shift-And-Add Constant Multipliers for FPGAs// accepted for presentation at the IEEE Symposium on Computer Arithmetic (ARITH), 2019,  [[http://martin-kumm.de/preprints/2019_ARITH_Dinechin.pdf|preprint]]  
 +  - J. Oppermann, P. Sittel, M. Kumm, M. Reuter-Oppermann, A. Koch, O. Sinnen, //Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling//, accepted for presentation at the European Conference on Parallel Processing (EUROPAR), 2019,  [[http://martin-kumm.de/preprints/2019_EUROPAR_Oppermann.pdf|preprint]] 
 +  - M. Hardieck, M. Kumm, K. Möller and P. Zipf, //Reconfigurable Convolutional Kernels for Neural Networks on FPGAs//, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Array (FPGA), Monterey February 2019, [[https://doi.org/10.1145/3289602.3293905|DOI]], [[http://martin-kumm.de/preprints/2019_FPGA_Hardieck.pdf|preprint]] (copyright ACM)
  - M. Hardieck, M. Kumm, P. Sittel and P. Zipf, //Constant Matrix Multiplication with Ternary Adders//, accepted for Presentation at the 25th IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. [[http://martin-kumm.de/preprints/2018_ICECS_Hardieck.pdf|preprint]]   - M. Hardieck, M. Kumm, P. Sittel and P. Zipf, //Constant Matrix Multiplication with Ternary Adders//, accepted for Presentation at the 25th IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. [[http://martin-kumm.de/preprints/2018_ICECS_Hardieck.pdf|preprint]]
  - P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, //ILP-based Modulo Scheduling and Binding for Register Minimization//, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 [[http://martin-kumm.de/preprints/2018_FPL_Sittel.pdf|preprint]] (copyright IEEE)   - P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, //ILP-based Modulo Scheduling and Binding for Register Minimization//, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 [[http://martin-kumm.de/preprints/2018_FPL_Sittel.pdf|preprint]] (copyright IEEE)
01Publications.1552893260.txt.gz · Last modified: 2019/03/18 08:14 by Martin Kumm
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